Figure 2 from Verilog synthesis of USB 2.0 full-speed device PHY IP | Semantic Scholar
Products-UFS-Silicon Motion
USB 2.0 extender control chipCH317 - NanjingQinhengMicroelectronics
Full Speed USB 2.0 Hub Controller - EEWeb
USB3250 | Microchip Technology
USB v2.0 Soft PHY and Device Controller
Webcam - Encore Electronics Inc.
ASMedia Demos USB 3.2 Gen 2x2 PHY, USB 3.2 Controller Due in 2019
USB 2.0 PHY IP Core Device Host OTG Hub in TSMC, 28HPC, 40LP /LL, UMC, 40LP, 28HPC, SMIC 14SF, SF, 55LL, 40LL - T2M-IP
Teledyne LeCroy - USB and USB Type-C® Electrical Test Solutions
Archimago's Musings: MEASUREMENTS: Computer USB port noise, USB hubs and the 8kHz PHY Microframe Packet Noise
Soft Mixed Signal Corporation USB 2.0 PHY IP Cores
USB 2.0 PHY Verification
USB 2.0 PHY IP core | Arasan Chip Systems
Mixed-Signal Verification for USB 2.0 Physical Layer IP
Synopsys IP Technical Bulletin: USB High Speed Inter-Chip (HSIC) IP: What is it? And why should I use it?
Figure 1 from Verilog synthesis of USB 2.0 full-speed device PHY IP | Semantic Scholar
USB to IDE/SATA Easy-Drive Cable USB 2.0 External Hard Drive Optical Drive Cable | eBay
The Next-Generation Interconnect | Mouser
PhyWhisperer-USB | Crowd Supply
USB2 Controller | Cadence
USB 2.0/HSIC PHY (Host/Device/OTG/Hub) - IP Solution - INNOSILICON
